Static random access memory (SRAM) is a type of electronic memory that is faster than standard dynamic RAM and does not need to be refreshed with a refresh pulse like other types of memory. SRAM is typically more expensive than other types of RAM and thus typically stores less data than dynamic RAM. SRAM is often utilized in cache memory applications. One significant advantage of SRAM is that it can be easily integrated into any CMOS logic process, hence it is typically the preferred memory choice for on-die integration with processors.
A semiconductor memory device, such as a SRAM, can be configured with bit cells that store one bit of data. The bit cells can be arranged in arrays and bit lines can connect the bit cells with a device or a sense amplifier that can read what value (a signal) that is stored in a bit cell, amplify the signal and discriminate the value stored by the memory cell to be either a logic 0 or a logic 1. The system can then transmit the logic value to a register, a processor or some other device or circuit. This read/amplify process is often performed by a sense amplifier. A typical SRAM sense amplifier can be a differential sense-amplifier consisting of cross-coupled inverters that are coupled to a pair bit-lines. A signal voltage may be developed on one of the bit-lines by the bit-cell either through actively discharging the bit-lines as in SRAMs or by charge sharing as in DRAMs.
Inherently, the pair of transistors in the sense amplifier circuit will often have a threshold voltage imbalance or a channel conductance imbalance. It can be appreciated that the offset voltage of a sense-amplifier can not be totally eliminated particularly when manufacturing thousands of silicone devices. Accordingly, the input voltage provided by the memory cell during a read operation to the sense-amplifier is effectively reduced by the offset voltage. Thus, if the stored voltage provided to the sense amplifier is less than the offset of a sense-amplifier, the memory cell cannot overcome the intrinsic offset and the sense-amplifier can resolve in the wrong direction causing an incorrect read of the value stored by the cell often called a read failure. Also, this inherent offset voltage requires a delay time to be introduced during the read to allow the stored cell voltage to swing the bit-lines to the offset voltage such that the sense amplifier will switch and an accurate read can occur.
It can be appreciated that such imbalances reduce the ability to accurately read the value stored by a memory cell. These imbalances can occur due to the systematic affects of producing a device, including the topology of manufacture and random affects such as dopant fluctuations and line edge roughness. Topology issues can be improved by careful layout of the sense-amplifiers. For example, the designer can utilize a matched common centroid style layout. Dopant fluctuations and line edge roughness cannot be eliminated since the variance of the mismatch between a pair of devices is inversely related to the gate area of the devices. Traditionally, this imbalance can be improved by increasing the area of the gate of the devices, however, this has additional negative impacts such as increased layout area. These imbalances can also create deviations in read out time and other important performance parameters.